Method and apparatus for clock tree solution synthesis based on design constraints

Abstract

A clock tree synthesizer calculates balanced cluster sets of nodes a particular level of a clock tree in a circuit description based on a set of available buffer types. Each balanced cluster set is tested to see if it meets a design constraint. If the design constraint is not met for a particular balanced cluster set, the particular cluster set is removed from consideration in the clock tree solution. For the cluster sets that do meet the design constraint, a cost associated with each cluster set is calculated. A balanced cluster set that has the lowest cost is selected for the clock tree solution. In one embodiment, the lowest cost balanced cluster set for one level in the clock tree forms the nodes for the next higher level in the clock tree, and the process is repeated at each level of the clock tree up to a root node. In another embodiment, the clock tree in the circuit description is modified with the lowest cost balanced cluster set for each level of the clock tree solution, wherein each cluster includes the buffer on which the cluster calculation was based.