The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2002
Filed:
Jan. 11, 1999
Fung Fung Lee, Milpitas, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An “incremental” timing analysis or simulation uses much of the results of a previous timing simulation. The previous timing results were obtained for a previous electronic design which was slightly modified by the designer. The portion of the design affected by the modification is identified and its timing is recalculated. The timing for the remainder of the design is left as is from the previous design. The boundaries of the region affected by the design modification may be determined by various methods. If the timing analysis is performed at an early stage in the overall design process, the method chosen may be relatively simple; i.e., it need not account for load, parasitic capacitance, etc.