Unbalanced clock tree for a digital interface between an ieee 1394 serial bus system and a personal computer interface (pci)

Abstract

A method of and apparatus for providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) bus. The digital interface system includes a number of functional elements in addition to a PCI interface element. Each of the functional elements and the PCI interface element receives a system clock signal via a clock tree. The clock tree derives individual clock signals from the system clock and provides these individual clock signals to each of the functional elements. The clock tree is balanced such that each clock transition occurs at each of the functional elements, other than the PCI interface element, at substantially the same time. Clock balancing is achieved through appropriate circuit layout and insertion of delay elements. The clock tree also derives a clock signal for the PCI interface element from the system clock signal. The portion of the clock tree which provides this clock signal to the PCI interface is not balanced with respect to the remainder of the clock tree. Rather, this portion of the clock tree is conditioned to provide a minimum of delay so as to comply with timing requirements for the PCI bus, such as data set-up and hold times associated with transitions in this clock signal. Accordingly, portions of the clock tree are balanced while at least a portion of the clock tree is not balanced.