Cache memory

Abstract

A cache memory system is described in which a content addressable memory and a cache RAM memory are provided. Each content addressable storage row has an associated hit line and an access enable line . An index decoder is provided for controlling cache replacement and cache maintenance operations. The hit line is used for passing both hit signals to the cache RAM and select signals generated by the index decoder . A gate operating under control of a multiplexer controller controls this dual-use of the hit line in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory . A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch . Upon a subsequent cycle the latched hit signal can be passed to an access enable line to permit a new TAG value corresponding to a second address B to be written to the content addressable memory . The cached data values from the first address A are now present within the cache memory system associated with a TAG value of the second address B. The dirty bit may be set to ensure that writeback occurs when the data value is removed from the cache memory thereby ensuring data integrity.