The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2002

Filed:

Jan. 27, 2000
Applicant:
Inventor:

Ko Noguchi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/362 ;
Abstract

The invention provides a semiconductor device that has sufficient device protection capability and besides allows integration of transistors with high density. The semiconductor device includes an NMOS transistor formed in a p-well on a p-type substrate, an n-well formed adjacent the p-well, and first and second protection elements connected to a gate electrode of the NMOS transistor. The first protection element is a pn diode formed from the p-well and an n diffusion region provided in the p-well and lets negative charges escape to the p-type substrate. The second protection element is a pn diode formed from the n-well and a p diffusion region provided in the n-well, and lets positive charges escape to the p-type substrate as pn junction leakage current between the n-well and the p-type substrate. In order to increase the area of the n-well that forms the protection element, the semiconductor device further includes a second p-well provided adjacent the first n-well, an n-type buried well formed below the second p-well, and a second n-well connected to the first n-well through the n-type buried well.


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