The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2002

Filed:

Sep. 11, 1998
Applicant:
Inventors:

Ichiro Hase, Kanagawa, JP;

Mitsuhiro Nakamura, Tokyo, JP;

Hidetoshi Kawasaki, Kanagawa, JP;

Shinichi Wada, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 3/1072 ; H01L 3/1109 ; H01L 3/10328 ; H01L 3/10336 ;
U.S. Cl.
CPC ...
H01L 3/1072 ; H01L 3/1109 ; H01L 3/10328 ; H01L 3/10336 ;
Abstract

A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.


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