Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground

Abstract

A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions. Next the dielectric layer is etched away to define a plurality of parallel dielectric strips and a number of dielectric islands are defined by photolithography using a mask of “POLY along a second direction” in the plurality of parallel strips. The dielectric layer is etched to define the plurality of islands. Finally, the stack structure and the thin gate oxide layer are etched to define gate regions of the matrix cells using said oxide island.