The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2002

Filed:

Apr. 01, 1999
Applicant:
Inventors:

Robert J. Volentine, Houston, TX (US);

Rahul G. Patel, Houston, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/206 ; G06F 1/208 ; G06F 9/32 ; G06F 9/42 ;
U.S. Cl.
CPC ...
G06F 1/206 ; G06F 1/208 ; G06F 9/32 ; G06F 9/42 ;
Abstract

A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack. By using non-general purpose registers to store data and return addresses, more general purpose registers are available for other reasons. The computer system advantageously permits the simulation of a conventional memory stack when main memory is not available to provide the conventional memory stack.


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