Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory

Abstract

A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor. The master processor effects data transfers from the slave processor to the memory over the data bus by reading a series of data from the slave processor onto the data bus, generating a series of memory addresses as the data are being read from the slave processor, and writing each data word into the memory as it appears on the data bus.