Timing controller having dependency memory, selection serialization component and reordering component for maintaining time dependencies in conversions between sequential and parallel operations using staging memory

Abstract

An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies associated with information and ensures the information is communicated and processed in an order that preserves the timing dependencies as the information is converted from parallel to parallel or parallel to serial operations. The present invention tracks the order in which information is loaded in a electronic hardware component and ensures that the information loaded into the electronic hardware component at a particular time is processed without interruption by information loaded at a different time. For example, the timing controller tracks the order in which texel information associated with a pixels parallelly loaded in a staging memory and issues electronic signals that cause the information loaded at a particular time to sequentially empty without interruption by information parallelly loaded in the staging memory at a different time.