Method and circuit for verifying configuration of programmable logic device

Abstract

A programmable logic device (PLD) including a non-volatile memory array for persistently storing configuration data, and a volatile memory array for temporarily storing the configuration data and controlling the various logic resources of the PLD to perform a user's logic operation. When the PLD is reset, an addressing circuit causes a column of non-volatile memory cells to transmit configuration data values to a corresponding column of volatile memory cells on a series of write lines. To verify that a configuration data value is successfully written from each non-volatile memory cell to a corresponding volatile memory cell, the data value transmitted on each write line is compared with the stored data value transmitted from each volatile memory cell on a corresponding read line. A control signal is generated when all of the data values transmitted on the write lines are equal to stored data values transmitted on corresponding read lines, thereby indicating that the configuration data values are successfully transferred to the column of volatile memory cells. The control signal is used to increment the address circuit, thereby addressing a next sequential column of non-volatile memory cells and associated volatile memory cells. Normal PLD operation is initiated when all configuration data is transferred.