Arrangements of interface logic, memory core, data shift and pad blocks for integrated circuit memory devices

Abstract

Rambus Dynamic Random Access Memory (DRAM) devices may have their functional blocks arranged effectively in an integrated circuit substrate. A first memory core block an interface logic block, a pad block, an input/output and internal clock signal generation block, a data shift block and a second memory core block are sequentially arranged in one axial direction of the substrate. Accordingly, the lengths of data lines for transmitting data between a data input/output unit of the input/output and internal clock signal generation block and the data shift block may be reduced so that loads on the data lines may be reduced, thereby allowing data transmission speed to be maintained and/or power consumption to be reduced. Moreover, the data lines need not be wired between pads in the pad block, which can prevent the width of the substrate from increasing. The distance between the first memory core block and the pad block may be equal to the distance between the pad block and the second memory core block so that devices can be accurately packaged on a module board.