The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2002
Filed:
Apr. 10, 2000
Shi-dong Zhou, Milpitas, CA (US);
Jack Siu Cheung Lo, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.