The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2002

Filed:

Apr. 30, 1999
Applicant:
Inventors:

Alessandro Camera, Savona, IT;

Paolo Sandri, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 ;
U.S. Cl.
CPC ...
H03K 3/00 ;
Abstract

An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided. According to the method, the input node is pulled-up to the level of a supply voltage at least when the input node receives a floating voltage, and such pulling-up of the input node is inhibited at least when the input node receives a high voltage signal whose level is higher than the level of the supply voltage.


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