The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2002
Filed:
Aug. 01, 2000
Philip A. Jeffery, Tempe, AZ (US);
Stephen G. Shook, Gilbert, AZ (US);
Semiconductor Components Industries LLC, Phoenix, AZ (US);
Abstract
A receiver circuit ( ) is programmable to operate with different logic family driver circuits ( ). The receiver circuit has two external configuration pins ( ) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit ( ) for an ECL application will require first and second configuration pins ( ) are connected to V —2 volts. To terminate the receiver circuit ( ) for a CML application will require the first configuration pin ( ) and the second configuration pin ( ) are connected to V . LVDS termination for the receiver circuit ( ) requires the first configuration pin ( ) and the second configuration pin ( ) are connected together. The configuration pins are external to a semiconductor package ( ) housing the receiver circuit.