The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2002

Filed:

Apr. 06, 1998
Applicant:
Inventors:

Shaw Wei Lee, Cupertino, CA (US);

Hem P. Takiar, Fremont, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A method of forming an integrated circuit package includes providing a flip chip integrating circuit die having a first plurality of contacts for electrically connecting the die to other elements. A second plurality of contacts for electrically connecting the integrated circuit package to external elements is also provided. A substrate for supporting the flip chip die and the second plurality of contacts is initially prepared. The substrate includes a connecting arrangement for electrically connecting the first plurality of contacts on the die to the second plurality of contacts. The method includes the step positioning the flip chip integrated circuit die and the second plurality of contacts on the substrate. With the flip chip die and the second plurality of contacts in position, both the first plurality of contacts on the flip chip die and the second plurality of contacts are simultaneously attached to the substrate thereby electrically connecting the die and the second plurality of contacts to the substrate. In one embodiment, a metal cap is attached to the integrated circuit package to cover and protect the die. In this embodiment, the metal cap may be used to provide a direct thermal path from the die to the external element to which the integrated circuit package is to the connected. An additional heat sink may also be attached to the package.


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