The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2002

Filed:

Jun. 19, 2000
Applicant:
Inventor:

Osamu Arai, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/16 ;
U.S. Cl.
CPC ...
H05K 1/16 ;
Abstract

A mounting structure of an integrated circuit device includes an integrated circuit device, a mounting board, a first solder bump, and a second solder bump. The integrated circuit device is mounted on the mounting board. The interposer board is interposed between the integrated circuit device and the mounting board. The first solder bump electrically connects the interposer board to the mounting board. The first solder bump is provided between the interposer board and the mounting board. The second solder bump buffers a stress. The second solder bump is provided between the interposer board and the mounting board.


Find Patent Forward Citations

Arai, Osamu. (2002). Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same (U.S. Patent No. 6362437). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6362437

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…