Load/store instruction control circuit of microprocessor and load/store instruction control method

Abstract

A load/store instruction control method of a microprocessor according to the present invention has a feature as follows. The circuit implements non-blocking cache which does not allow a pipeline process of a microprocessor to stop even if a cache miss by load/store instructions occurs. When the load instruction for a no-write allocate area directly storing a store-data to a lower layer memory in a cache hierarchy at time of a cache-miss initiates the cache-miss, and a subsequent store instruction initiates the cache-miss for the same cache line as that of the preceding load instruction, during a refill process of the DCACHE by the preceding load instruction or after the refill process, the store-data by the subsequent store instruction is stored to a corresponding cache line. Consequently, unconformity of data such as only the lower layer memory in the cache hierarchy holds a new data and only the DCACHE holds an old data does not occur.