System bus read address operations with data ordering preference hint bits for vertical caches

Abstract

A method for preferentially ordering the retrieval of data from a cache line of a cache within a vertical cache configuration. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval based on the cache configuration. The set of bits is then sent along with the read request via the address bus to the first cache. The cache directory is check to see if a “hit” occurs (i.e., the data is present in that cache). If the data is present, a modified cache controller having preference order logic or a preference order logic component interprets the set of bits and directs the retrieval of the requested data from the cache line according to the preferred order for that cache. If no hit (i.e., a miss) occurs, the read request and the preferred order set of bits are sent to the next level cache. In one embodiment, a single set of bits is utilized. The preference order logic encodes the set of bits with the preference order of the next level cache when a miss occurs, prior to sending the read request and the set of bits to the next level cache. When all levels of cache result in a miss, the read request is sent over the system bus with the preference order set of bits being encoded for the system wide preference.