Mpeg-2 transport demultiplexor architecture with non-time-critical post-processing of packet information

Abstract

An appatatus for enhancing transport packet demultiplexing and distribution in a digital transport demultiplexing system that inputs a stream of digital multimedia transport packets is provided. The demultiplexing apparatus performs the demultiplexing operation by transferring data packets into and out of circular data queues. These circular queues comprise a contiguous block of memory which are defined by a queue starting address, a queue size, a read pointer, and a write pointer. When data packets are written to and read from a circular queue, the sequential addressing of the queue will automatically rollover from the highest memory location within the queue to the lowest memory location when the sequential addresses move through the circular queue. The addressing of the various queues and sharing of a transport stream bus is handled by a memory arbiter and queue manager.