The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2002

Filed:

Jun. 30, 1998
Applicant:
Inventors:

Masayuki Inoue, Yokohama, JP;

Yukio Sato, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 ;
U.S. Cl.
CPC ...
H04J 3/06 ;
Abstract

A receiving apparatus with intermittent receiving for receiving a TDMA SIG is disclosed. The receiving apparatus receives a FRQ reference SIG to control a voltage controlled OSC for generating a system clock and receives a TDMA synchronizing SIG to control the phase of a TDMA timing SIG to establish the reference FRQ synchronizing and the TDMA synchronizing. To save a power consumption in the sleep interval during the intermittent receiving, it is stopped to supply a supply power to a d/a converter supplied with the FRQ control data to supply a FRQ control voltage to the voltage controlled OSC. Just before an intermittent receiving interval, that is, the end of the sleep mode, the supply power to the d/a converter is supplied and the TDMA timing is compensated by calculation from the sleeping interval and the FRQ of the self-oscillation of the voltage controlled OSC. The TDMA timing may be not compensated but receives the TDMA synchronizing SIG to control the TDMA synchronizing if the phase difference in the TDMA timing is within the range of the correlator. The FRQ reference SIG may be received to compensate the FRQ and phase of the system clock and the TDMA synchronizing timing may be compensated by calculation from the sleeping interval and the FRQ of the self-oscillation of the voltage controlled OSC.


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