Test structure for determining the properties of densely packed transistors

Abstract

The present invention advantageously provides a test structure and method for determining the distinct characteristics of each transistor arranged in a densely packed configuration with other transistors. Formation of the test structure first involves forming gate conductors according to the configuration of the semiconductor topography whose device properties are being determined. That is, closely spaced gate conductors having relatively small lateral widths, i.e., physical gate lengths, are formed above a semiconductor substrate. All of the gate conductors except the one being tested are then etched from above the substrate. Source/drain implants which are self-aligned to the opposed sidewall surfaces of the gate conductor retained above the substrate are forwarded into the substrate. Absent the other gate conductors, the resulting source/drain regions may each have a larger lateral width greater than the distance between the pre-existing gate conductors. As such, the lateral width of contacts formed through an interlevel dielectric to the source/drain regions may be made significantly less than the lateral width of each source/drain region. Therefore, the contacts, and hence the contact openings, may be formed without being concerned that portions of the gate conductor might be etched and that the contacts might electrically communicate with the gate conductor.