Cellular trench-gate field-effect transistors

Abstract

A cellular trench-gate field-effect transistor comprises a field plate ( ) on dielectric material ( ) in a perimeter trench ( ). The dielectric material ( ) forms a thicker dielectric layer than the gate dielectric layer ( ) in the array trenches ( ). The field plate ( ) is connected to the source ( ) or trench-gate ( ) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter ( ) because of its presence on the inside wall of the trench ( ) without acting on any outside wall ( ). The array and perimeter trenches ( ) are sufficiently closely spaced, and the intermediate areas ( ) of the drain drift region ( ) are sufficiently lowly doped, that the depletion layer ( ) formed in the drain drift region ( ) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage. This arrangement reduces the risk of premature breakdown that can occur at high field points in the depletion layer ( ), especially at the perimeter of the cellular array.