Emulating branch instruction of different instruction set in a mixed instruction stream in a dual mode system

Abstract

A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instruction includes a separate branch instruction and a branch control instruction, while in the second instruction set, a second type branch instruction includes only a branch instruction. The processor is optimized to handle the first instruction set so that the branch instruction is arrangeable in a program sequence so that an execution unit in the processor can compute a branch target address based on the branch control instruction without a latency penalty. The first type branch instructions also include a folded-compare format, while the second type branch instructions have separated compare and branch instructions. To handle the second type branch instructions, they may be converted into first type branch instructions so they can be executed in emulated form by the processor.