The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2002

Filed:

Jun. 23, 2000
Applicant:
Inventor:

Takato Shimoyama, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/500 ; G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/500 ; G11C 1/604 ;
Abstract

According to one embodiment, an asynchronous static random access memory (SRAM) circuit ( ) can provide reduced power consumption and high-speed access. An SRAM circuit ( ) may include address registers ( and ) that can store a write address from one write operation and output the stored write address during a subsequent write operation. A data register ( ) may also be included that can store write data from one write operation and output the stored write data during a subsequent write operation. Memory cells of a memory cell array ( ) may be selected according to a pulse word signal PW. A pulse word signal PW can be generated in response to transitions in an address and transitions in a write enable signal /WE. Hit address comparators ( ) within address registers ( and ) in combination with a hit AND gate ( ) can activate a HIT ALL signal when a stored write address matches an applied read address. When the HIT ALL signal is activated, an output circuit ( ) can output stored write data instead of an output from a sense amplifier circuit ( ).


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