Cmos small signal switchable, impedence and voltage adjustable terminator network

Abstract

A CMOS terminator circuit for connection to a network can be fabricated and used within for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's corresponding input terminal circuit control nfet and pfet mirror devices whose bodies are also connected respectively to lower and upper level supply power to control each of their turn on voltages. The reference path swing voltage of the terminator is established as being that approximating an ideal 50 ohm split resistor terminator. An adjustment section enables the voltage to be adjusted up and down to re-center the An adjustment section enables adjustment of the impedance of the terminator, with fine tuning of the terminator to a desired reflection for the nets and adjustment of the center voltage which allows tune out of any process mistracking and re-centering of the terminator voltage, so that maximum input signal voltages can be obtained without creating skew between the zero and one logic levels.