The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2002
Filed:
Jul. 11, 2000
David J. Klein, Duluth, GA (US);
Prashant Shamarao, Atlanta, GA (US);
Integrated Device Technology, Inc., Santa Clara, CA (US);
Abstract
Integrated circuit output buffers include primary and secondary pull-down transistors and an output signal line electrically coupled to a drain of the primary pull-down transistor and a drain of the secondary pull-down transistor. A preferred control circuit is also provided. The control circuit turns on the primary pull-down transistor during first and second consecutive portions of a pull-down time interval and uses a signal fed back from the output signal line to control the timing of when a gate of the secondary pull-down transistor is electrically connected to a drain of the secondary pull-down transistor during the first portion of the pull-down time interval and also control the timing of when the gate electrode of the secondary pull-down transistor is electrically connected to a source of the secondary pull-down transistor during the second portion of the pull-down time interval. A pull-down portion of the control circuit may include a gate pull-up transistor having a drain electrically connected to the drain of the secondary pull-down transistor and a source electrically connected to a gate of the secondary pull-down transistor, and a gate pull-down transistor having a drain electrically connected to the gate of the secondary pull-down transistor and a source electrically connected to a source of the secondary pull-down transistor. These gate pull-up and pull-down transistors can be utilized to selectively turn on the secondary pull-down transistor during a first leading portion of a pull-down time interval and then turn off the secondary pull-down transistor during a second trailing portion of the pull-down time interval.