The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2002
Filed:
Feb. 28, 2000
Akira Hiroki, Osaka, JP;
Shinji Odanaka, Hirakata, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate ( ) under a source diffusion layer ( ) is lower than the impurity concentration on a source side of a p-type impurity diffusion layer ( ). Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage. Consequently, according to the present invention, a semiconductor device which can be operated at a low power consumption is realized.