The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Jun. 16, 2000
Derek R. Curd, Fremont, CA (US);
Hy V. Nguyen, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The output buffer includes a pullup transistor and a pulldown transistor for applying an output signal to an I/O pad. When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Also, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor.