The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Jul. 18, 2000
Ramon Coronel, Torrance, CA (US);
Karen A. Fucik, Redondo Beach, CA (US);
Peter S. Yoon, Torrance, CA (US);
David W. Y. Lee, Torrance, CA (US);
Richard B. Sherwood, Palos Verdes Estates, CA (US);
Donald G. Heflinger, Torrance, CA (US);
TRW Inc., Redondo Beach, CA (US);
Abstract
A wafer-scale module includes a plurality of stacked wafers, each having a thin semiconductor layer disposed on a surface of the wafer, a plurality of wafer-scale integrated (WSI) circuits formed on the semiconductor layer and a plurality of nodes formed on the semiconductor layer. Each node provides an optoelectronic interface to an axial optical waveguide for high-speed optical interconnectivity between the WSI circuits and other integrated wafer circuit devices of the stack. A top plate is included and is disposed on the plurality of stacked wafer devices. A base plate, included for purposes of thermal dissipation, is disposed opposite the top plate such that the plurality of stacked wafers are sandwiched between the top plate and the base plate and all are assembled.