The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Jul. 16, 1999
Claudio Brambilla, Concorezzo, IT;
Manlio Sergio Cereda, Lomagna, IT;
Giancarlo Ginami, Bergamo, IT;
SGS-Thomson Microelectronics S.r.L., Agrate Brianza, IT;
Abstract
A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer ( ) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer ( ); c) forming over the whole integrated circuit a first layer of conductive material ( ); d) forming over the first layer of conductive material ( ) a layer of insulating material ( ); e) removing the layer of insulating material ( ) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material ( ) which in the memory cell array area is separated from the first layer of conductive material ( ) by the insulating material layer ( ), while outside the memory cell array area is directly superimposed over said first layer of conductive material ( ); g) inside the memory cell array area, defining first strips ( ) of the second layer of conductive material ( ) for forming rows ( ) of the memory cell array ( ), and outside the memory cell array area defining second strips ( ) of the second layer of conductive material ( ) for forming interconnection lines ( ) for electrically interconnecting the rows ( ) of the memory cell array with a circuitry ( RD), said defining the second strips ( ) providing for selectively etching the first and second layers of conductive material ( ) outside the memory cell array area by means of a first mask (MASK ), and said defining the first strips ( ) providing for selectively etching the second layer of conductive material ( ), the layer of insulating material ( ) and the first layer of conductive material ( ) inside the memory cell array area by means of a second mask (MASK ).