The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2002

Filed:

Apr. 17, 1995
Applicant:
Inventors:

Hugo W. K. Chan, Rancho Palos Verdes, CA (US);

Arnold H. Silver, Rancho Palos Verdes, CA (US);

Assignee:

TRW Inc., Redondo Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D 5/12 ; C23C 1/408 ; H01L 3/924 ;
U.S. Cl.
CPC ...
B05D 5/12 ; C23C 1/408 ; H01L 3/924 ;
Abstract

High temperature superconductive (HTS) integrated circuits can be fabricated in three ways according to the invention. First, a planar multiple layer HTS integrated circuit is fabricated using multiple HTS layers. The layers include altered regions which have been bombarded using ion implantation to destroy superconductivity of the altered regions without interrupting the lattice structure of the altered regions. Second, a planar multiple-layer HTS integrated circuit includes upper and lower HTS layers, each including central and opposing regions. A first implant energy is used to destroy superconducting properties of the opposing regions of the lower HTS layer without interrupting the lattice structure. A second implant energy is used to destroy superconducting properties of a top portion of the central region to define a contact. Third, a HTS integrated circuit is formed from a single HTS layer using three ion implantation steps and ions having first, second and third energies and range.


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