The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2002
Filed:
Dec. 02, 1999
Edward G. Palmer, Melbourne, FL (US);
Charles M. Newton, Palm Bay, FL (US);
Harris Corporation, Melbourne, FL (US);
Abstract
A multi-chip module has an integral capacitor element embedded within the substrate and comprises a plurality of substrate layers forming a multi-chip module substrate. The substrate has a cut edge and forms at the cut edge a bondable edge. A via is formed in the substrate, and a dielectric capacitive material fills the via for a plurality of substrate layers and defines a multilayer capacitor. The multilayer capacitor and via are positioned at the bondable edge and connects to the bondable edge. In one aspect, the via having the dielectric capacitive material is positioned at the cut edge, and includes a conductive material filling at least a portion of the cut via to form the bondable edge. The dielectric capacitive material and bondable edge form a junction surface. A signal trace can be formed on a substrate layer and connected to the capacitor to form a DC blocking capacitor structure. A ground line can be formed on one substrate layer and engage the capacitive material. A signal trace can be formed on one of the substrate layers and engage the bondable edge to define a decoupling capacitor structure.