The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2002

Filed:

Jan. 26, 1999
Applicant:
Inventors:

Edmund Chen, Sunnyvale, CA (US);

Glenn William Connery, Sunnyvale, CA (US);

Claude Hayek, Huntington Beach, CA (US);

Paul Sidenblad, Cupertino, CA (US);

Assignee:

3Com Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/324 ;
U.S. Cl.
CPC ...
G06F 1/324 ;
Abstract

A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, peripheral component events are coalesced. A peripheral component such as, for example, a network interface card generates a first interrupt when the number of coalesced peripheral component events meets a quantity threshold. In the present embodiment, a peripheral component driver such as, for example, a network interface card driver then services the first peripheral component event. In one embodiment of the present invention, the peripheral component then services any existing coalesced peripheral component event (or events) that has not yet generated a respective interrupt. The service of peripheral component events is monitored for determining the quantity of peripheral component events not serviced. The number of peripheral component events not serviced is then used to vary the quantity threshold. The new quantity threshold is then used to determine when a second interrupt is to be generated. As a result, the present invention optimizes the generation of interrupts, reducing the frequency with which interrupts are generated, and minimizing the CPU overhead associated with the servicing of interrupts.


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