The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2002
Filed:
Nov. 17, 1999
Alexis Shishkoff, Raleigh, NC (US);
Barry L. Stakely, Snowcamp, NC (US);
TranSwitch Corporation, Shelton, CT (US);
Abstract
A phase/frequency detector includes two D-Q flip-flops, an OR gate, and an exclusive NOR (XNOR) gate. The phase/frequency detector is used in conjunction with a clock dejitter PLL where the underflow and overflow flags from a FIFO are coupled to the inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of the XNOR gate. The Qb output of each flip-flop is coupled to the D input of the respective flip-flop. The recovered clock signal is coupled to the clock input of the first flip-flop and the output of the VCXO is coupled to the clock input of the second flip-flop. The SET input of the first flip-flop is coupled to the overflow flag and the RESET input of the first flip-flop is coupled to the underflow flag. The SET input of the second flip-flop is coupled to the output of the OR gate and the output of the XNOR gate is passed through the filter to the input of the VCXO. When the phase is locked, the output of the XNOR has a 50% duty cycle which causes the voltage across the filter to remain constant which maintains a steady VCXO output frequency. The FIFO will either underflow or overflow if the recovered clock and the VCXO run at different speeds. In this case, the flip-flops generate correction pulses that will drive the PLL filter voltage to the point where the VCXO is running at the correct frequency.