The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2002

Filed:

Dec. 07, 1998
Applicant:
Inventor:

Brian L. Brown, Sugar Land, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

A DRAM is disclosed that is capable of performing a rapid write-followed-by-read operation. In a preferred embodiment , the DRAM includes a plurality of memory banks ( ), a global write bus ( ), and a global read bus ( ). The global write and read buses ( and ) are coupled to each memory bank ( ) by an associated local read/write circuit ( ). In an initial write operation to a first memory bank ( ), input data on the global write bus ( ) are latched in a first local read/write circuit ( ) associated with the first memory bank ( ). In a subsequent read operation to a second memory bank ( ), as data are output from the second memory bank ( ) onto the global read bus ( ) via a second local read/write circuit ( ), the first local/read write circuit ( ) is simultaneously writing the latched input data into the first memory bank ( ).


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