The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2002
Filed:
Jan. 04, 2001
Jose M. Soltero, Sherman, TX (US);
Dale P. Stein, Sherman, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch. In a preferred embodiment, a bus-hold integrated circuit servicing Insulated Gate FET digital switches can be operated from either of two distinct ranges of supply voltage (V ). The magnitudes of the holding currents for the higher range of V are nearly the same as those for the lower range of V . This characteristic is achieved by changing the resistance in the feedback path of the bus-hold circuit according to the applied V . Resistance is increased by turning off wider channel IGFETs that are connected in parallel with narrower channel IGFETs when the higher range of V is applied. When the lower range of V is applied the wider channel IGFETs are switched on and the resistance of the holding current path is decreased in proportion to the decrease in V .