The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2002

Filed:

Jul. 22, 1997
Applicant:
Inventors:

Chuen-Der Lien, Los Altos Hills, CA (US);

Kyle W. Terrill, Campbell, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.


Find Patent Forward Citations

Lien, Chuen-Der. (2002). Strapping via for interconnecting integrated circuit structures (U.S. Patent No. 6350645). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6350645

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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