The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2002
Filed:
Jun. 01, 1998
Dojun Rhee, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A recursive decoder for decoding a binary codeword of length N having a first stage, at least one intermediate stage, and a final stage. The first stage including a plurality of decoder groups, each of the groups having a plurality of sets of first and second decoders, each of the first and second decoders having a plurality of inputs and an output, a plurality of adder groups, each of the adders having a first input connected to the output of the first decoder of one of the sets and a second input connected to the output of the second decoder of one of the sets, and an output. The at least one intermediate stage including at least one decoder group, each of the at least one decoder group having a plurality of sets of first and second comparators, each of the first and second comparators having inputs and an output, the inputs of each of the comparators in a first intermediate stage connected to the outputs of one of the plurality of adder groups, at least one adder group, each of the adders having a first input connected to the output of the first comparator of one of the sets and a second input connected to the output of the second comparator of one of the sets, and an output, the inputs of each of the comparators in other than the first intermediate stage connected to the outputs of one of at least one adder group. The final stage, including a comparator having inputs and an output, the inputs connected to the outputs of a final intermediate stage.