Semiconductor memory device capable of independent selection of normal and redundant memory cells after programming of redundant address

Abstract

A redundancy determining unit pre-stores a defective memory cell address in a normal memory cell array, and selects a redundant memory cell instead of a normal memory cell in a normal operational mode. The redundancy determining unit selects a designated redundant memory cell row in response to an address signal when a test mode signal and a redundancy identification address signal are activated. If the test mode signal is activated whereas the redundancy identification address signal is inactivated, a replacement operation for the normal memory cell and the redundant memory cell is stopped.