The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2002
Filed:
Sep. 29, 2000
Masahiko Ogino, Hitachi, JP;
Takao Miwa, Hitachinaka, JP;
Toshiya Satoh, Kanasagou-machi, JP;
Akira Nagai, Hitachi, JP;
Tadanori Segawa, Hitachi, JP;
Akihiro Yaguchi, Iwama-machi, JP;
Ichiro Anjo, Koganei, JP;
Asao Nishimura, Kokubunji, JP;
Takumi Ueno, Mito, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.