The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2002
Filed:
Oct. 09, 1998
Frederick H. Fischer, Lehigh, PA (US);
Agere Systems Guardian Corp., Orlando, FL (US);
Abstract
A test device for testing inter-device connections of field programmable gate arrays (FPGAS) by using the FPGAs themselves during testing to form a shift register. Particularly, the shift register comprises flip-flops and buffers interconnected by the actual FPGA inter-device or inter-device connections under test. A control circuit generates an input test pattern which is serially input into one end of the shift register and read out of the other end. The input pattern and the output pattern are compared to determine if they match. If they match, there are no faults through the interconnections used in the shift register. The shift register also may be bidirectional such that the input and output patterns are read in and out at the same terminal.