Direct-digital synthesizers

Abstract

A direct-digital synthesizer for generating a waveform includes a digital accumulator fed by a phase increment word and a series of clock pulses for successively adding the phase increment word to produce a series of N bit phase words. A table or trigonometric engine produces sine and cosine digital signals related to the M most significant bits of the phase word produced by the accumulator. A feedback loop is fed by truncation error words comprising at least a portion of N-M least significant bits of the N bit phase words producing truncation error compensation words. The feedback loop includes a digital filter. The feedback loop includes a digital filter. The feedback loop including the digital filter provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC. The truncation error response has a transfer function comprising the term (1−az ) where: z is the discrete time frequency variable and a is a unity or non-unity weighting n factor. One such filter includes an adder fed by the truncation error words and a storage device fed by the clock pulses and by the truncation error words for producing at an output thereof the truncation error words delayed by each one of the clock pulses fed thereto. The adder is fed by the output of the storage device to produce an algebraic sum of the truncation error words fed to the adder and the delayed truncation.