The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2002
Filed:
Jul. 10, 1998
Lennart Mathe, San Diego, CA (US);
Daniel T. Macek, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
A low power sample rate converter adapted for use with a telecommunications system transceiver. The sample rate converter includes a first circuit that provides an input signal characterized by a first sample rate and a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, samples in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, samples in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal providing a rate-converted version of the input signal as an output signal in response thereto. In a specific embodiment, the delayed version of the input signal is delayed by one sample with respect to the input signal. The sample rate converter further includes a counter that is clocked by a first periodic signal. The first periodic signal has a frequency related to the first sample rate by a predetermined fraction. The counter is cleared by a second periodic signal having a second frequency equivalent to the first sample rate. The counter produces a counter output at the first frequency. In the preferred embodiment, the predetermined fraction is ⅓ and the first predetermined coefficient is equivalent to the sum of 1 and the counter output. The second predetermined coefficient is equivalent to the difference of 2 and the counter output. The fourth circuit includes an adder for adding the first signal and the second signal and providing the output signal in response thereto. The predetermined transfer function is represented by the following coefficient sequence: [1 2 3 2 1].