The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2002
Filed:
Aug. 04, 1999
Wayne Yeung, San Francisco, CA (US);
Chiakang Sung, Milpitas, CA (US);
Myron W. Wong, Fremont, CA (US);
Khai Nguyen, San Jose, CA (US);
Bonnie I. Wang, Cupertino, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Joseph Huang, San Jose, CA (US);
In Whan Kim, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.