Methods for fabricating microelectronic device interconnects with spun-on glass regions

Abstract

An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa. A third insulation layer is formed on the substrate, covering the planarized SOG region, and portions of the second and third insulation layers overlying the second mesa are then removed to expose a portion of the second mesa. An interconnecting region is formed n the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second mesa. Microelectronic devices so formed are also discussed.