The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2002

Filed:

Aug. 23, 2000
Applicant:
Inventors:

Michael J. Follingstad, Edina, MN (US);

James W. Conroy, Prior Lake, MN (US);

Peter W. Adams, Minneapolis, MN (US);

Assignee:

ADC Telecommunications, Inc., Minnetonka, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 1/200 ;
U.S. Cl.
CPC ...
H01R 1/200 ;
Abstract

The present disclosure relates to high density patching system. The system includes a card housing having a front end positioned opposite from a rear end. The card housing includes top and bottom walls extending between the front and rear ends. The top and bottom walls define opposing sets of top and bottom slots. The patching system also includes a plurality of patch cords including patch plugs each having a width W and a height H . The patching system further includes a plurality of jack access cards adapted to be mounted in the card housing, and a rear interface module positioned at the rear end of the card housing. The jack access cards include circuit boards having top and bottom edges adapted to fit within the sets of top and bottom slots defined by the card housing. The jack access cards also include a plurality of card edge contacts positioned at a rear of each circuit board. The jack access cards further include front interface pieces having heights H that are greater than two times the height H , and widths W that are each less than two times the width W . The front interface pieces each define upper and lower patch plug ports that are vertically spaced along the height H of each front interface piece. The upper and lower patch plug ports are sized and shaped to receive only a single one of the patch plugs at a time. The rear interface module includes a single row of card edge connectors adapted for providing electrical connections with the card edge contacts of the jack access cards. The rear interface module also includes an array of rear connectors including upper and lower rows of rear connectors. The array of rear connectors is electrically connected to the card edge connectors by a flexible circuit board. The rear interface module also includes a frame that spaces the card edge connectors from the rear connectors. The frame includes a rear wall defining upper and lower rows of openings that respectively receive the upper and lower rows of rear connectors.


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