The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2002
Filed:
Sep. 11, 2000
Applicant:
Inventor:
Francis B. Heile, Santa Clara, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/908 ; H03K 1/9177 ;
U.S. Cl.
CPC ...
G11C 1/908 ; H03K 1/9177 ;
Abstract
A programmable logic array integrated circuit device includes regions of programmable logic, regions of memory, and a programmable network of interconnection conductors for selectively conveying signals to, from, and between the regions of logic and memory. The memory regions are usable as content addressable memory. Circuitry is provided for facilitating programming of the memory in content addressable mode.
Heile, Francis. (2002). Programmable logic devices with improved content addressable memory capabilities (U.S. Patent No. 6344989). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6344989
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile