The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2002
Filed:
Feb. 29, 2000
Applicant:
Inventor:
Eiji Io, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/18234 ;
Abstract
A CMOS transistor and a memory cell transistor are formed without causing deterioration to reliability and performance. A step of covering a memory cell region with an HTO film and forming sidewalls in the CMOS transistor while exposing a diffusion region of the CMOS transistor, a step of depositing titanium, and a step of reacting the diffusion region with the titanium, forming a titanium silicide in the CMOS, transistor source and drain are provided.
Io, Eiji. (2002). Method for fabricating semiconductor device including memory cell region and cmos logic region (U.S. Patent No. 6344386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6344386
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile