Method and device for local clock generation using universal serial bus downstream received signals dp and dm

Abstract

A method and device is disclosed for generating a local clock signal CLK X ( ) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters ( ) are used to determine a number of periods of a free-running high frequency clock signal ( ) contained within in a known number of bit periods of the downstream received bit-serial signal ( ). The counter values are divided by the known number of bit periods of the received bit-serial signal ( ) to determine a bit period of the received bit-serial signal ( ). The local clock signal ( ) may be phase-locked with the received bit serial signal ( ). The local clock period is updated on an ongoing manner by downstream known received traffic.